Embedded System Design with Microblaze and Vitis IDE

Using Xilinx Vivado Design Suite and Vitis 2020.2

What you'll learn
Embedded System Design flow with Xilinx Vitis 2020.2
Designing Embedded System using Microblaze Soft Processor
Development of C applications for Microblaze Devices
Software and Hardware Debugging
Handling Interrupts in Microblaze based designs
Understanding Xilinx Drivers

Requirements
Understanding of Digital Electronics
Fundamentals of Computer Architecture

Description
A faster Reconfigurable system makes FPGA a prominent choice for a large set of applications, but Hardware alone is incomplete without smart software synchronizing all the events fruitfully to achieve the desired Application. This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Microblaze based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Microblaze to felicitate performance measurement.

The Microblaze is an FPGA-based Soft Processor capable of executing single instruction per cycle with few exceptions. The MicroBlaze interconnect is reconfigurable capable of communicating with a large set of peripherals to fit most of the medium-scale applications. It allows configuration of cache size, pipeline depth, peripherals, memory management unit, and bus interface suitable to fit different application requirements. As systems complexities are growing day by day, Microblaze will play central role in the non-Zynq based FPGA families whereas it will be the best light-weight alternative working in tandem with the Zynq hard processor for Zynq and Ultrascale based FPGA families.

Who this course is for
Anyone wish to build expertise in Xilinx Microblaze Devices with Xilinx Vivado and Vitis IDE
Embedded System Design with FPGA Soft Processors

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