Cadence SPB Allegro and OrCAD v17.40.002-2019 Hotfix Only (x64)

Cadence SPB Allegro and OrCAD v17.40.002-2019 Hotfix Only Release Notes
-ADW DBEDITOR Adding a property to EDM root classification does not add to the child classifications
-ADW FLOW_MGR Cannot see any flow files to select in EDM flow manager
-ADW FLOW_MGR Message regarding error detected in the CPM file (FM-107) on opening or creating new project
-ADW FLOW_MGR Error on opening and creating new project (FM-107)
-ADW FLOW_MGR Opening ECAD designs throw bad configuration error after Java upgrade to 1.8.0_231.
-ADW FLOW_MGR ERROR (FM-107) on opening project
-ADW LIBDISTRIBUTI fetch_dump stops responding intermittently when using HTTP over high latency networks
-ADW LIBDISTRIBUTI Incomplete copy of principal.jar during lib_dist_client/fetch_dump.
-ALLEGRO_EDITOR CROSS_SECTION Cross-section chart 'Draw options' - 'Layer Gradient Draw'/'Background Gradient Draw' not working properly
-ALLEGRO_EDITOR CROSS_SECTION Release 17.4-2019: Color Draw - Gradients is not working in via list viewer
-ALLEGRO_EDITOR DFM DesignTrue mask to trace and mask to shape checking not performing correctly
-ALLEGRO_EDITOR DFM DesignTrue DFF annular ring fiducial to antipad checks not working.
-ALLEGRO_EDITOR DFM DesignTrue DFM: plated slot annular ring pad to mask checks inconsistent
-ALLEGRO_EDITOR DFM Thieving vias are treated as antenna vias in DesignTrue DFF copper features antenna via checks
-ALLEGRO_EDITOR DFM Design performance slow when DFF checks are turned on.
-ALLEGRO_EDITOR DRC_CONSTR Pad-Pad Direct Connect waived constraint reappears after DRC update
-ALLEGRO_EDITOR DRC_CONSTR Differential pair static phase is yellow, but nets are routed
-ALLEGRO_EDITOR DXF Compose Shape: Imported DXF shape broken into arcs
-ALLEGRO_EDITOR EDIT_ETCH Unwanted cline segment is added when neighboring cline is slided
-ALLEGRO_EDITOR EDIT_ETCH Cannot create unique via structure
-ALLEGRO_EDITOR INTERFACES PDF Export contains extra page for bond wires
-ALLEGRO_EDITOR MANUFACT Silkscreen is different for rounded rectangle pads and rectangular pads
-ALLEGRO_EDITOR MANUFACT 'Clear soldermask pad' option is not working in 'Auto Silkscreen'
-ALLEGRO_EDITOR MANUFACT Autosilk bug causes WARNING(SPMHA1-36): Illegal LINE identifier -- while running a symbol update
-ALLEGRO_EDITOR MULTI_USER UDbidRange error in Symphony team design
-ALLEGRO_EDITOR MULTI_USER Changes are not updated for some users in a team in Symphony
-ALLEGRO_EDITOR MULTI_USER Symphony: Changes not saved with 'rejected by server' and 'Waiting for a UDbidRange' messages
-ALLEGRO_EDITOR MULTI_USER Symphony not writing back to the master
-ALLEGRO_EDITOR PAD_EDITOR Padstack Editor should be updated for Slot Hole to prevent Secondary Drill tab from being shown.
-ALLEGRO_EDITOR PLACEMENT Quickplace fails to place components with the ALT_SYMBOL property
-ALLEGRO_EDITOR SCRIPTS Commands in two script files executed in the incorrect order
-ALLEGRO_EDITOR SCRIPTS Replay of script to set paper size in PDF OUT shows "Value for field is not legal"
-ALLEGRO_EDITOR UI_FORMS Route Automatic form flicker when adding a new pass to Routing Passes tab
-ALLEGRO_EDITOR UI_FORMS Visibility filters for pin numbers of chip-on-board wire bond die bump
-ALLEGRO_EDITOR UI_GENERAL Memory leak and performance degradation opening 1000 .dra databases
-ALLEGRO_EDITOR UI_GENERAL PCB Editor slows down during opening of 1000 databases
-ALLEGRO_EDITOR UI_GENERAL When using Pop Mirror funckey, component jumps to origin in OrCAD PCB Designer
-ALLEGRO_EDITOR UI_GENERAL Highlight command replaces assigned color output and Dehighlight does not get it back
-ALLEGRO_EDITOR UI_GENERAL Allegro_html environment variable cross-probing behavior different in release 17.4-2019 than 17.2-2016
-ALLEGRO_EDITOR VALOR Release 17.4-2019: Cannot generate ODB++ output with the Expert Suite bundle licenses
-ALLEGRO_LIB_CRT CORE Variable DFA_DEV_CLASS is not being exported into the Allegro footprint
-APD EDIT_ETCH 'Route' - 'Slide' performs erratically when fillets are present where the cline sizes transition
-CAPTURE BACKANNOTATE Release 17.4-2019: Design Sync does not work on design with occurrence properties
-CAPTURE BACKANNOTATE Design Sync not working on hierarchical designs.
-CAPTURE BACKANNOTATE Unable to Design Sync Board to Schematic
-CAPTURE DRC Unable to delete DRC Markers in release 17.4-2019
-CAPTURE DRC 'Show DRC output' in DRC window does not remember NONE option
-CAPTURE DRC Cannot delete DRC-markers in schematic
-CAPTURE DRC Cannot remove DRC markers in the Design rule check GUI
-CAPTURE DRC Capture release 17.4-2019: Delete existing DRCs does not work
-CAPTURE NETLIST_ALLEG Differences shown in design sync dialog for a CM-enabled project even if schematic and board are in sync
-CAPTURE NETLIST_ALLEG Design Sync giving the same report even if the connection exist
-CONCEPT_HDL CORE DE-HDL crashes on renaming signal on an interface with a second tab with the symbol open
-CONCEPT_HDL CORE No architecture declaration in the source file message while doing Generate View for Hierarchical split symbol .
-CONCEPT_HDL CORE DE-HDL stops responding on Copy-Paste of properties from one instance to another
-CONCEPT_HDL CORE The database version tag '<schemaVersion>' is not updated for release 17.4-2019
-CONCEPT_HDL INTERFACE_DES DE-HDL crashes when drawing a wire to a netgroup
-CONCEPT_HDL OTHER DE-HDL menu related message not clear
-CONCEPT_HDL OTHER Launching Project Manager (projmgr.exe) takes time to get license from license server
-CONSTRAINT_MGR INTERACTIV Constraint Manager: region deleted even on clicking 'NO'
-CONSTRAINT_MGR OTHER Clicking on CSet link in Show Constraints form does not go to CSet in CM
-CONSTRAINT_MGR OTHER Relative prop delay values in 17.4-2019 do not show pin pairs on choosing Analyze from popup on the Match Group
-CONSTRAINT_MGR OTHER Constraint Manager crashes when clicking on the cell for the MAX_PARALLEL rule
-CONSTRAINT_MGR SCHEM_FTB Running Import Logic on an out-of-sync board does not bring in the constraints and connectivity
-CONSTRAINT_MGR UI_FORMS CSet names from the 'Value Filter' not sorted alphabetically
-CONSTRAINT_MGR UI_FORMS Re-launching CM does not retain the last state
-CONSTRAINT_MGR UI_FORMS UI issues with CM in release 17.4 - Expanded state of WS is not getting preserved on applying object filters.
-PSPICE ENVIRONMENT PSpice AA Topics are missing from Learning Resources for release 17.4-2019
-PSPICE NETLISTER Netlister not able to pass local parameter in specific case for complex hierarchical designs
-PULSE UNIFIED_SEARC 3D STEP models are not downloaded for some providers
-SCM NETLISTER Error (SPCOHD-198) regarding incorrect signal syntax on netlisting
-SIP_LAYOUT DIE_ABSTRACT_ SiP Layout uses 25GB memory for showing IC details and does not finish command for showing details
-SIP_LAYOUT INTERACTIVE Batch Layer Compare: cannot check quadrant against another symmetrical quadrant in same design using Mirror/Rotate
-SIP_LAYOUT ORBITIO_IF Support component height translation between OrbitIO and Allegro layout editor
-SIP_LAYOUT STREAM_IF Streaming out a design with embedded dual-sided symbol (eBar) causes inadvertent mirrored symbol in .sf file
-SIP_LAYOUT STREAM_IF Stream out causes crash
-SIP_LAYOUT WIREBOND Wire Bond push and shove tools not working in a constraint area.
-SYSTEM_CAPTURE CROSSPROBE Cross-probe from System Capture to Allegro PCB Editor loop back issues
-SYSTEM_CAPTURE EDIT_SEARCHRE Unable to edit a net name on canvas after modifying it using an external editor
-SYSTEM_CAPTURE EDIT_SEARCHRE Find Results: pop-up Edit menu does not appear for user property with NULL value
-SYSTEM_CAPTURE PROJECT_EXPLO Navigating signals from the Navigation viewer jumps to the project viewer
-SYSTEM_CAPTURE UI Incorrect message to resolve conflict during part packaging
-SYSTEM_CAPTURE UI Error message from the "Violation Window" does not resolve '%S'
-SYSTEM_CAPTURE WIRING Visible net properties are not getting moved with the circuit move