VSD - Static Timing Analysis - I

VLSI - Essential timing checks

What you'll learn
Understand various STA checks for timing closure
Able to do a quality analysis for real designs
Know-how on how real STA works in industries, something which you will not find in any books
Step-by-step and structured timing analysis
Requirements
Knowledge on physical design flow will be good to have
If not, no worries. This course will take you from basics to advanced in a structured manner and create an interest in physical design world
Description
Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I - Essential timing checks. This course will give an eagle's eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

Who this course is for
Course starts from basic timing path to advanced latch checks, so basics of flipflops should be enough

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